In conventional electronic devices such as portable terminals, there may be two kinds of operation mode, for example, a normal operation mode causing a relatively large power consumption and a stand-by mode saving a power consumption. For example, a portable telephone device performs communications and data input-output operations in the normal operation mode and queues for receiving in the stand-by mode. Such portable telephone device is provided with a non-volatile memory such as a flash memory and a volatile memory such as an SRAM and a DRAM, which are used for different purposes, taking into account different features of performances (or specification) of those memories. The non-volatile memory is used mainly for holding data for a long term. The SRAM exhibits a high speed access and has a low power consumption, for which reason the SRAM is used for storing data which receive frequent accesses in the stand-by mode in addition to the normal mode. The DRAM needs refresh operations and causes a relatively large power consumption but has a large capacity, for which reason the DRAM is used mainly for providing a data storing area in the normal mode. For example, data such as telephone numbers are stored in the non-volatile memory, because those data are needed to be held even when a battery power is lost. Data stored in the SRAM are data which receive frequent accesses and are prevented from disappearing in a stand-by state, such as data used for communication to a base station in the stand-by state. A relatively large amount of data such as display data are stored in the DRAM because those data are allowed to be disappeared in the stand-by state.
Japanese laid-open patent publication No. 10-124200 “portable information terminal” describes one example of the conventional configurations, wherein a normal operation mode and a stand-by mode (or suspend mode) are provided for a portable information terminal including SRAM and DRAM as described above. In accordance with the configuration described in this publication, a high speed execution of a system software appears in the normal operation mode, while in the stand-by mode, the data area is switched from the DRAM to the SRAM, for subsequent low speed execution of a power control program which has been stored in a ROM (read only memory) and the SRAM. Examples of the control methods for having accesses to both the SRAM and the DRAM with the same configuration are described in Japanese laid-open patent publication No. 6-139371 “microcomputer”, and Japanese laid-open patent publication No. 1-166147 “memory control circuit”. In accordance with the prior art described in Japanese laid-open patent publication No. 6-139371, a signal processor has accesses to both the SRAM and the DRAM, wherein a memory, to which an access is intend to be made, is discriminated. If an access-object is the SRAM, then all bits of the address are outputted one time. If the access-object is the DRAM, then row and column addresses are outputted with time-division. In accordance with the configuration described in Japanese laid-open patent publication No. 1-166147, there are further provided a refresh counter which generates a refresh address for the RAM and an address switching circuit, so that a multiple address and a non-multiple address are switched depending on the access-object, and further a refresh operation to the DRAM is automatically executed.
There are other conventional semiconductor memory devices with both the SRAM and the DRAM, wherein the SRAM with a small capacity is combined to the DRAM with a relatively large capacity, so that the SRAM is used as a cache memory of the DRAM. In accordance with this configuration, data read operations from the DRAM and data write operations into the DRAM are taken place through the SRAM which allows relatively high speed accesses, resulting in high speed accesses being realized. In this configuration, however, only an address space of the DRAM is recognized from outside of the semiconductor memory device. Independent accuses to both the SRAM and the DRAM are not possible as described in the above publications.
Meanwhile, the other conventional semiconductor memory device utilizes a technique for saving a device function by replacing a defective bit line or a defective word line with any defectiveness caused in the manufacturing processes, into a bit line or a word line in a redundancy memory cell array provided in the same semiconductor memory device. The redundancy memory cell array may be provided in the same memory chip as the memory cell array which should be saved, or in a redundancy chip which is provided over a mounting board and is separated from the memory cell array which should be saved, wherein the mounting board has a plurality of memory chips or a packaged chip. Japanese laid-open patent publication No. 8-16486 “defect-saving LSI and memory device” describes one example of the conventional saving configuration for replacing the defect caused in the DRAM chip in a module into a redundancy SRAM chip in the module.